The UART Wildcard supports any baud rate produced by the above formula. The actual baud rate produced differs from that requested by a small error owing to rounding of an internal divisor. The two lowest order bits in the SPCR control register, named SPR1 and SPR0, determine the data exchange frequency expressed in bits per second; this frequency is also known as the baud rate. When PE is set (equal to one), the most-significant bit in each byte transmitted will be a parity bit that is either set or cleared by the serial port automatically in order to achieve even or odd parity. The PDQ Board's two serial ports support limited use of generating a parity bit. For seven data bits with a parity bit, M would be cleared (equal to zero), and PE would be set in order to make the most-significant bit of a normal eight-bit byte be used by the serial port as a parity bit.

The words port and channel are used interchangeably to refer to a serial communications link. Owing to hardware constraints, if modem handshaking is needed on UART channel 1, then channel 1 must be configured for RS232, and channel 2 cannot be configured for RS232 communications. Serial 2 is implemented by a software UART in the controller’s QED-Forth Kernel that uses two of the processor’s PortA I/O pins to generate a serial communications channel. The default serial routines used by the onboard kernel assume that full duplex communications are available, so you cannot use the RS485 protocol to program the controller. This ability to exchange messages means that the SPI is capable of full duplex communication. So long as the error between the actual baud rate and that specified is less than 1.5% (or the error between transmitter and receiver is less than 3%) there should be no communication errors. Rather, the transmitter and receiver must be communicating using a known baud rate, or bit frequency. Both the local and remote UARTs must be configured for the same baud rate. The local and remote must share a common ground, so all serial cables include at least one ground conductor. Because a single pair of conductors is used for both transmission and reception, RS485 is useful for multi-drop applications in which a master communicates with multiple slave serial devices, or nodes.

They should generally not be needed, except if you use long cables, multiple RS485 devices, and resistive termination. Bias termination - Using resistive termination decreases noise immunity, particularly if the cable is loaded with many devices. In the most common multi-drop RS485 protocol, one computer is designated as a master and the rest of the computers or devices on the serial bus are designated as slaves. Because all of the serial I/O routines on the PDQ Board are revectorable, it is very easy to change the serial port in use without modifying any high level code. The serial output at the UART idles at the logic high (mark) level. Serial data is shifted out least-significant-bit first. To ensure that no two devices drive the network at the same time, it is necessary that each slave device be able to disable its own RS485 data transmitter. RS485Init() configures PORTJ to ensure that bits 0 and 1 are outputs, and disables both RS485 transmitters, leaving the Serial1 and Serial2 RS485 channels in receive mode.

The PDQ Board controls the Serial1 and Serial2 RS485 transceivers with bits PJ0 and PJ1, respectively, of PORTJ of the processor. 1 or 2 to specify Serial1 or Serial2, respectively, and clears the appropriate PORTJ bit to place the transceiver in receive mode. Then reading the data that was received (by reading the SPDR) or initiating a new data transfer (by writing to the SPDR) automatically clears the SPIF flag. This chapter describes those drivers, and presents code that makes it easy to configure the SPI for different data transfer rates and formats. The SPIF is set when a data transfer is complete, and is cleared by a read of the SPSR status register, followed by a read or write to the SPDR data register. There are three flag bits implemented in the SPSR (SPI status register). These steps greatly reduce the chance that the communicating devices might be damaged by contention on the SPI bus. If you are using the QScreen as a slave device and require the /SS signal for your external SPI hardware, configure one of the Port A pins on the Field Header as an input pin.

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